The basic criteria for judging a system specification are the same for a computer-based control system as for analog equipment. There are, however, additional items in a computer system which even an experienced designer may sometimes overlook. It is therefore advisable for the specification writer to have a checklist of items available or to consult the procurement documents of a successful control system

A complete outline of the sample specification is presented in Table 8 4. In this section a sample specifica­tion is presented and discussed section by section. The sample shows what should be included in a specification that requires the manufacturer to provide computer sys­tems programs but not the control software. Not all the items shown m the sample will appear in every specifica­tion. Many systems will not require double precision and floating-point hardware, memory protect, automatic re­start, etc On the other hand, the sample specification does not include special-purpose electronics that might be supplied by the computer manufacturer

We stress the point that the following specimen is for illustration only. It would not be used for an actual procurement because

1. There will usually be some items that are undergoing improvement and field testing of which the specification writer is unaware. A “functional” specification for such items may allow a supplier to offer equipment that would not meet strict performance specifications but is actually best suited to the application.

2. The detailed requirements in the specimen represent performance at or near the state of the art In the interest of a lower pnce and better competition, these should be relaxed wherever possible to correspond to the needs of the plant

3. System suppliers are continually developing execu­tive programs and adding applications programs to their software packages. By using as much of the supplier’s proven control software as appropriate to the application, the designer can realize a considerable project cost saving

4. Design engineers often prefer to evaluate computer speed by finding the running time of a bench-mark program that includes arithmetic, logic, transfer, and mput/output instructions in about the proportions that they will occur in the actual application. Besides providing a good functional criterion for acceptance, this method can reveal deficiencies in computer architecture that might not show up if only the operating speeds of the individual computer functions were analyzed.

8-6.1 Introductory Sections

The specification should begin with a short descnption of the reactor the computer is to be associated with and what the computer is expected to do. The bidder must be given a thorough and unambiguous concept of the whole system. Following this summarizing statement, the broad specifications of the computer itself should be described. A list of the major equipment should be presented in the order in which the equipment is described in the body of the specification.

The sample section below shows how the introductory sections of the system specification might be written.

SPECIFICATION FOR XPR-1 COMPUTER SYSTEM

SUMMARY

This specification details the requirements for the digital — computer system to be installed as an integral part of the XPR-1 instrumentation and display system The computer system will operate on-line to the reactor and provide the necessary equipment for reactor systems support, analysis, control, and reporting

This application supports the operation of XPR-1 (Experimental Power Reactor Number One), a 1000 MW(e) nuclear facility designed for the generation of electric power The computer system will support this facility by providing data acquisition, analysis, control, display, and reporting The reactor is characterized by both on—off and continuous data-acquisition and control processes On—off operations are typified by block valves, start—stop pump, supply utilities, etc Continuous monitoring and control is applied to neutron flux, temperature, flow, etc The success of this installation will depend on the reliability of the system, thus, meeting the reliability and quality assurance requirements is important

1.0 GENERAL DESCRIPTION

This specification describes a general-purpose digital computer of the binary, core-memory, parallel, single-address type with indirect and indexed addressing The computer system is to be used as the basis of a real-time control system performing control functions in the operation of a nuclear power reactor The computer system is required to respond to both analog and digital inputs, provide analog control signals, and store data in on-line bulk storage Operator communication is by keyboard and interactive cathode — ray tube display

2.0 MAJOR EQUIPMENT LIST

2 1 24-bit general-purpose computer with 16K of core memory.

2 2 250K word disk storage unit

2 3 100 line-per-minute line printer

2.4 300/100 character-per-second paper-tape reader/punch.

2 5 Two 21-in color cathode-ray-tube display consoles

2 6 An analog input facility for 2000 points.

2.7 A digital input facility for 2000 points

2 8 An analog output facility for 20 points

8-6.2 Central Processor

The requirements of the central processor are then listed. An acceptable range of word lengths, the result of a detailed analysis of data-handling and computation needs, is stated. The instruction set, memory requirements, and the

Table 8.4—Specification Outline (Summary Description)

5 13 Error control 5 14 Write lock 5 2 Line printer

5 2 1 Print speed 5 2 2 Number of columns 5 2 3 Character spacing 5 2 4 Character size 5 2 5 Character registration 5 2 6 Character set 5 2 7 Character replacement 5 2 8 Line spacing 5 2 9 Line registration 5 2 10 Paper handling

5.2.11 Ribbon

5 2 12 Printer cabinet soundproofing 5 2 13 Paper storage 5 3 Paper-tape reader/punch 5 3 1 Speed 5 3 2 Code

5 3 3 Tape take up and supply

5 4 Display—Alphanumeric and graphic

5 4 1 Display area 5 4 2 Phosphor 5 4 3 Spot size

5 4 4 Random positioning time

5 4 5 Positioning repeatability

5 4 6 Jitter

5 4 7 Resolution

5 4 8 Contrast ratio

5 4 9 Brightness

5 4 10 Vector data format

5 4 11 Vector end point registration

5 4 12 Vector writing rate

5 4 13 Character plot

5 4 14 Character sizes

5 4 15 Number of characters displayed

5 4 16 Aspect ratio

5 4 17 Intensity

5 4 18 Light pen

5 4 19 Keyboard

5 4 20 Memory

5 4 21 Enclosure

6 Software

6 1 Executive 6 2 Compiler 6 3 Assembler

6 4 Correction program 6 5 Diagnostic and utility programs 6 6 Input/output programs 6 7 Maintenance programs 6 8 Delivery form

6 9 Documentation

7 Environmental and miscellaneous characteristics

7 1 Temperature 7 2 Humidity

7 3 Power 7 4 Enclosure 7 5 Spare parts 7 6 Documentation 7 7 Reliability

7 8 Quality-assurance program

other items in this section must reflect the type of application whether it emphasizes data acquisition, data analysis, or process control Taken together, these items should also force the bidders to confine their offerings to heavy-duty industrial-grade equipment to the exclusion of light laboratory computers, desk computers, and machines designed for scientific or business data processing

The central-processor section of the sample specifica­tion is as follows

3.0 CENTRAL PROCESSOR

З 1 Core Memory

3 11 Word Length

The computer shall utilize a basic word length of 24 bits excluding memory parity and memory protect

3.1 2 Word Capacity

A minimum of 16,384 twenty-four-bit words of core memory shall be provided The computer shall be capable of field expansion to at least

32,768 words 3 1.3 Speed

The maximum read/restore memory cycle time shall not exceed 2 0 /isec 3 14 Parity

Memory parity shall be provided for each word in memory such that each transfer to, or from, memory is checked for correct parity An error shall cause an interrupt signal which identifies the location of the word in error 315 Protect

Memory protect shall be provided for each word in memory This bit shall be selectable under program control for each individual word When an at­tempted violation is detected by the computer, an interrupt signal shall be generated which identifies the location of the attempted violation

3 2 Arithmetic Unit

3.2 1 Hardware Arithmetic

Hardware arithmetic shall be provided to perform (1) single precision, (2) double precision, and (3) floating-point add, subtract, multiply, and divide

3.2 2 Execution Times

Execution times shall not exceed those listed below

	Single precision, fisec	Double precision, jusec	Floating point, Msec
Add	40	40	20
Subtract	4 0	4.0	20
Multiply	20	20	100
Divide	30	30	100

3.3 Addressing

3.3.1 Direct

The computer shall be capable of directly ad­dressing a minimum of 2048 memory locations.

3.3.2 Indirect

Multilevel indirect addressing shall be provided with a capability of reading a minimum of 32,768 memory locations. Each level ot indirect address shall add no more than one (1) memory cycle to an instructions execution time.

3 3 3 Indexing

At least three (3) dedicated index registers shall be provided

3 4 Priority Interrupts

At least 32 channels of multilevel hardware interrupt shall be provided such that any higher priority channel can interrupt the processing of a lower priority channel Each interrupt shall have a separate dedicated memory location (32 total) that contains space for the necessary instruc­tions to initiate a device service routine All interrupts except those assigned to the stall alarm and the power fail safe shall be capable of being individually turned on or off under program control

3 5 Direct Memory Access

A minimum of two (2) direct-memory-access (DMA) ports shall be provided Each port’s transfer rate shall be at least 500,000 twenty-four-bit words per second Multiplex capability for two channels at 250,000 twenty four-bit words per port shall be provided

3.6 Clocks

Two (2) basic clocks shall be provided, a real-time clock and an interval timer. The real-time clock shall have a basic frequency of 60 Hz. The interval timer shall have a crystal-controlled rate of 100 kHz with an accuracy of ±10 Hz per day. Additional registers shall be provided with the interval timer such that they can be loaded from memory under program control and incremented or decremented by the clock The timer shall provide an output signal (for use as an interrupt) when the register reaches zero.

3.7 Stall Alarm

A stall alarm shall be provided that detects machine looping or stalls. The method used shall be discussed in the response to bid.

3.8 Operator’s Console

An operator’s console shall be provided and shall include a tabletop working surface of at least 200 sq in.

3.8.1 Console Switches

A data entry switch corresponding to each bit in a word shall be provided. It shall be possible to enter data “manually” to “memory” and to all registers that are software accessible.

3.8.2 Display

The console shall provide for the display of the status of the following registers or their equivalent А-register (A-accumulator)

В-register (B-accumulator)

P-register (program counter)

I-register (instruction register)

M-register (memory address register)

X-register (index register)

In addition, the console display shall provide a run—halt indicator, an mput/output hold indi­cator, and a protect—violation indicator.

3.8.3 Console Teletype

A KSR-35 teletype, or equivalent heavy-duty machine, shall be interfaced to the computer for use as an operator’s console.

8-6.3 Process Input/Output

The process input/output are the communicating links between the plant and the computer. The multiplexer and converters are first specified individually as to number of

points, speed, and addressing. Then, because of the com­plex interrelations involved, a tendency toward functional specification is introduced, the requirements are placed on the entire input or output channel rather than on individual components Since the input/output list (see sample below) is a summary of many of the process interfaces, it is important to make sure that the two sets of requirements agree

The input/output sample specification is as follows

4 0 PROCESS INPUT/OUTPUT

4.1 Input/Output Channels

In addition to the direct-memory-access channel specified in Sec. 3 (Central Processor), the system shall provide a shared input/output (I/O) bus such that all peripheral devices can communicate directly with the computer

4.2 Speed

The I/O bus shall support I/O transfers at rates up to 30 kHz.

4.3 Input/Output Parity

I/O parity shall be provided. The system shall provide a hardware parity test for each I/O transfer and indicate all I/O parity errors by program interrupts

4.4 Input/Output Addressing

Capability for addressing a minimum of sixty-four (64) peripheral devices shall be provided. Each bidder shall indicate the standard I/O assignment by logical device number and hardware address number for all standard peripherals available for the computer

4.5 Digital Inputs

4.5.1 Capacity

The system shall provide for the input of at least two thousand (2000) binary signals. These signals take the following form

Type a 500 twelve (12)-bit voltage words. Type b 1000 one-bit binary voltages.

Type c 500 one-bit contact closures.

4.5.2 Logic Definition

Voltage inputs shall be positive true (1 = positive voltage). The following voltage range is required

+0.5 volt -0.0 volt +2.7 volts -0.0 volt

(The values specified are for conventional diode — transistor logic. It should be noted that high-level logic with improved noise immunity has recently become available from several sources. This high — level logic should be used whenever possible.) Contact signals shall be input as closure true Speed

The minimum transfer rates are as follows

50 type a inputs 1 kHz/channel

450 type a inputs 0 033 Hz/channel 48 type b inputs 30 kHz/channel (2 computer words)

952 type b inputs 1 Hz/channel (40 computer words)

500 type c inputs 0 5 Hz/channel (21 computer words)

4.6 Analog Outputs

4 6.1 Number of Channels

Twenty (20) channels of digital-to-analog output shall be provided

4.6.2 Output Range

The output shall be +10 volts full scale

4.6.3 Data Input

The data input shall be twelve (12) bits per channel fully buffered

4.6.4 Accuracy and Linearity

Accuracy and linearity shall be at least ±0 05% of full scale 5 mV

4.6 5 Monotonicity

The converter output shall be monotomc for each input bit change from negative (—) to positive (+) full scale.

4 6 6 Sag

The output sag shall be less than 1 mV/qsec

4.6 7 Slew Rate

The analog output rise time (10 to 90%) shall be 3 Msec or less for a full scale step change (digital) at the input.

4.6.8 Settling Time

The time required to settle to within 0.1% of the final value shall be less than 15 Msec for a full-scale step change (digital) at the input with 1000 pF capacitive load

4.6.9 Short-Circuit Capability

The output amphfier(s) shall be capable of sustain­ing a continuous short circuit to ground without damage.

4.7 Analog Inputs

The analog input system shall consist of a multiplexer(s), sample and hold amplifier(s), and an analog-to-digital converter It shall include all interface hardware required to make the analog system a functional part of the computer system.

4.7.1 Multiplexer

4.7.1.1 Input Switches

The input switches shall be field-effect transistors, either junction type (J-FET) or m e t a 1-ox і de-sem і со n d uctor (MOSFET). If MOSFET devices are sup­plied, each gate shall be protected from oxide rupture due to overvoltage.

4.7.1.2 Number of Channels

A minimum of 1000 input channels shall be provided. At least 500 channels shall be low level, the balance shall be high level (as defined in Sec. 4.7.1.6).

4.7.1.3 Input Configuration

Each input shall be differential-guarded (three-wire). All three inputs shall be commutated. A minimum of two (2) levels of subcommutation shall be pro­vided to isolate the input.

4.7.1.4 Sampling Rate

The following minimum sampling rates shall be provided

100 low-level channels, 5000 chan­nels/sec

100 high-level channels, 2500 chan­nels/sec

400 low-level channels, 10 channels/ sec

400 high-level channels, 10 channels/ sec

4.7.1.5 Input Impedance

The input impedance of an “off” channel shall be greater than ten (10) megohms when measured differentially or from either input to ground.

4.7 1.6 Full-Scale Input Voltage

The full-scale input range of the multi­plexer shall be as follows

Low-level inputs, ±10 mV High-level inputs, ±10 volts

4.7.1.7 Crosstalk

Crosstalk shall be less than ±0.01% of full scale on any channel when a 100% over­load is present on an adjacent channel.

4 7 18 Scatter

Channel-to-channel scatter shall be less than ±0.1% of full scale for the same input on all channels.

4.7.1.9 Common-Mode Rejection

Common mode rejection shall be at least 120 db from direct current to 60 Hz with a balanced source impedance. It shall be at least 85 db from direct current to 60 Hz for a 500-ohm unbalanced source impedance.

4 7 110 Maximum Common-Mode Voltage

The multiplexer(s) shall be capable of sustaining ±20 volts direct current or peak alternating current on any input without damage to the input switches and without turning on deselected channels.

4.7.1.11 Full-Scale Output Voltage

The full-scale output voltage shall be ±5 volts or greater for both low — and high — level inputs.

4.7.1.12 Address Modes

Three separate address modes shall be provided random, sequential, and dwell. Each mode shall be program initiated. The random access mode shall permit an external binary word to select any address at random. The sequential mode shall provide a fixed sampling pattern and be capable of operating from an internal or external clock. The dwell mode preselects one channel for continuous duty.

4.7.2 Analog-to-Digital Converter

4.7.2.1 Number of Bits

The converter shall provide 12 bits of information with the most significant bit representing the sign of the input data.

4.7.2.2 Conversion Speed

The total conversion time shall not ex­ceed 10/asec including sample time and hold time.

4.7.2.3 Aperture Time—Sample and Hold

The converter shall incorporate a sample and hold amplifier. The aperture time shall be 100 nsec or less.

4.7.2.4 Acquisition Time—Sample and Hold

The acquisition time shall not exceed 6 psec for a full-scale step input.

4 7 2 5 Sag—Sample and Hold

The permissible decay during hold shall be less than 4 of the least significant bit (lsb).

4.7.2.6 Accuracy

The transfer accuracy of the converter shall be at least ±0.05% ±’/ lsb

4.7.2.7 Monotonicity

The converter output shall be monotomc increasing (or decreasing) for a change from plus (+) to minus (-) full scale and from minus (-) to plus (+) full scale.

4.7.2.8 Linearity

The deviation from a straight line through plus (+) and minus (—) full scale shall not exceed ±0.1% t1/ lsb

4.7.2.9 Overscale indicator

One bit shall be provided to indicate an overscale input.

4.7.2.10 Display

A front-panel display that indicates the output word status shall be provided for troubleshooting purposes.

8-6.4 Standard Peripherals

Whereas the input/output includes the peripherals that are peculiar to process control systems, the standard peripherals include those items and their interfaces which are common to most computer systems The characteristics of each item depend on the application and often are compromises between programming efficiency and hard­ware cost This is particularly true of punched-card units and line printers. Only by experience can one estimate accurately the tradeoff between the programmers’ man­hours and the machine cost involved.

Although cathode-ray-tube (CRT) displays are be­coming more common, they have been used ш computers in so many different ways that no standard set of design criteria has yet been developed. It is therefore necessary, once the display content and formats have been decided on, to make a detailed analysis of the required data storage and transfer rates These are then related to the known capabilities of currently marketed hardware. Equipment to display both alphanumeric and graphic data should be studied carefully, a raster method may be required for one and beam steering for the other, with the result that two separate spares are needed if standby redundancy is a system requisite.

The standard-peripherals section of the sample specifi­cation is given below. The intermediate-speed bulk storage device may be either disk or drum, the specifications being quite similar. The disk was arbitrarily chosen for the example.

5. STANDARD PERIPHERALS

5.1 Disk Memory

A disk memory shall be interfaced to the computer. It shall utilize a fixed head per track design. The read/record heads shall not contact the disk surface.

5.1.1 Capacity

Disk capacity shall be a minimum of 12,000,000 bits.

5 1.2 Access Time

Worst case access time shall be less than or equal to 16 msec.

5.1.3 Error Control

Parity generation and error detection shall be provided for all transfers to and from the disk. The nominal error rate shall be no greater than 1 bit lost m 10* 0 data transfers.

5.1.4 Write Lock

Write lock shall be provided for at least 50% of the total storage capacity.

5.2 Line Printer

A line printer shall be interfaced to the computer. The printer will be used for on-line printing of alphabetic, numeric, and symbolic data.

5.2.1 Print Speed

Print speed shall be not less than 300 lines per minute.

5.2.2 Number of Columns

A minimum of 132 print positions (columns) across shall be provided.

5.2.3 Character Spacing

Character spacing shall be ten (10) characters to the inch (horizontally). The maximum cumulative error shall not exceed ±0.02 in. for the 132- column line.

5.2.4 Character Size

Nominal character size shall be 0.1 in. (vertically) by 0.066 in. (horizontally).

5.2.5 Character Registration

Vertical and horizontal registration shall be within a ±0 005-in tolerance.

5.2.6 Character Set

The following 64 characters shall be supplied A, В, C, D, E, F, G, H, I, J, K, L, M, N, О, P, Q, R, S, T, U, V, W, X, Y, Z, 1, 2, 3, 4, 5, 6, 7, 8, 9, ф, (,), ‘,

…….. /, -, +, &, L $, <, >, t,’, ", =, #, @, , %,

‘Л. ІЛл

5.2.7 Character Replacement

It shall be possible to individually remove and replace characters.

5.2.8 Line Spacing

Line-to-lme spacing shall be 6 lines per inch.

5.2.9 Line Registration

Line-to-lme registration shall be within ±0.005 in. nonaccumulative.

5.2.10 Paper Handling

The printer shall accept paper widths ranging from

2.5 to 18.5 in. The paper used shall be standard Z-fold sprocket feed. It shall be possible to use

6- part paper (multiple copy).

5.2.11 Ribbon

The printer ribbon shall be equipped with an automatic reversal feature.

5.2.12 Printer-Cabinet Soundproofing

The printer cabinet shall contain sound-deadening material with a minimum thickness of l/ in.

5.2.13 Paper Storage

Both input and output paper storage shall be provided.

5.3 Paper-Tape Reader/Punch

A paper tape reader/punch shall be interfaced to the computer

5.3.1 Speed

The system shall read/punch at a minimum speed of 300/100 characters per second.

5.3.2 Code

The system shall read and punch the standard

7- level ASCII code as described in ASA Standard X3.18-1967.

5.3.3 Tape Take-Up and Supply

The system shall utilize fanfold paper tape. Both supply and take-up bins for fanfold tape shall be supplied.

5 4 Display—Alphanumeric and Graphic

Two independent displays shall be interfaced to the computer. Each display system consists of a cathode-ray — tube assembly, vector generator, character generator, light pen, keyboard, and interface electronics.

5.4.1 Display Area

The display screen shall be not less than 19 in. across the color cathode-ray tube (diagonal or diameter measurement). The usable viewing area shall be not less than 12 sq in. All specifications shall be met everywhere in this area.

5.4.2 Phosphor

The CRT shall utilize a P22 phosphor (or equiv­alent) The faceplate shall have a boned safety shield installed.

5.4.3 Spot Size

The display-spot size shall not exceed 0.020 in. at the half-light points.

5.4.4 Random-Positioning Time

It shall be possible to display points at random. The maximum time required to position the beam and settle to within one spot width of the final position shall not exceed 16 /іsec.

5.4.5 Positioning Repeatability

The display-spot position repeatability shall not exceed ±0.3% of full scale independent of the previous position.

5.4.6 Jitter

The display-spot jitter shall not exceed ±0.2% of full scale over a time interval of 1 hr.

5.4.7 Resolution

The resolution in the x and у directions shall be ten (10) binary bits. The matrix defined is 1024 by 1024 points

5.4.8 Contrast Ratio

The contrast ratio for black and white shall be no less than 4 1 in an ambient light level of 20 ft-c.

5.4.9 Brightness

The brightness shall exceed 20 ft-lamberts in an ambient light level of 8 ft-c.

5.4.10 Vector Data Format

The display shall provide at least two (2) vector formats, one long and one short. Short vectors are defined as less than 1 m. The time required to display short vectors shall not exceed 5 Msec It shall be possible with the long-vector mode to specify either (inclusive) relative vector or absolute vector. In relative mode the x and у coordinates of the end point are given and the vector is drawn from the previous point. In absolute mode the x and у coordinates are specified and the vector is drawn relative to the origin of the position matrix.

5.4.11 Vector End-Point Registration

End-point registration shall be within ±0 03 5 in

5.4.12 Vector Writing Rate

The time required to write a vector shall be less than 50 msec regardless of length. The display intensity shall be constant irrespective of the length of the vector.

5.4.13 Character Plot

The character generator shall contain at least sixty-four (64) alphanumeric and symbolic charac­ters. The character set shall include those charac-

ters listed for the line printer in Sec. 5.2.6. The character generation time shall not exceed 10 jusec.

5 4.14 Character Sizes

At least two (2) programmable character sizes shall be provided.

5.4.15 Number of Characters Displayed

The display system shall be capable of displaying and refreshing not less than 1500 characters (50 Hz refresh rate)

5.4.16 Aspect Ratio

The character aspect ratio shall be not less than 4 3 (height to width) or greater than 3 2

5.4.17 Intensity

Three programmable intensity levels shall be sup plied for each primary color (red, blue, and green).

5.4.18 Light Pen

A photoelectric light pen shall be supplied for each display. It shall transmit an interrupt signal to the computer whenever a point on the display screen, within view of the pen, is intensified

5.4.19 Keyboard

An alphanumeric and symbolic keyboard shall be supplied with each display such that all defined characters can be entered from the keyboard. In addition, a function keyboard with at least 16 keys shall be supplied. A keyboard overlay that permits the selection of at least eight (8) different function groups shall be provided for all function keys. A separate overlay shall be supplied for each of the eight groups. Overlay code names shall not be supplied

5 4.20 Memory

A local refiesh memory capable of storing one frame of data shall be supplied with each display.

5 4 21 Enclosure

The display system shall be enclosed in a console cabinet. It shall have a table extending in the front below the cathode-ray tube. The cathode-ray tube shall be tilted slightly toward the back to facilitate operator viewing